Many mobile or portable electronic devices, such as cellular telephones, portable digital assistants or PDAs, laptops, and other like devices, which operate on battery power. Thus, reducing power consumption is an extremely important issue, as consumers increasingly demand longer operating times between recharging.
One known method for reducing or minimizing power consumption in portable electronic devices is to place the device in a low-power standby or sleep-mode in which power to all unnecessary circuitry is reduced or removed while the device is idle. One circuit that is commonly powered down is a DC linear voltage regulator such as a low dropout (LDO) regulator. Voltage regulators are used to provide a stable, regulated output voltage to other circuits and elements in the portable electronic device. Frequently, these devices include distributed shared memory (DSM) having dual on-chip voltage regulators including an active regulator that is turned-OFF in standby mode and a standby regulator. In addition to being powered down while the chip or device is in sleep-mode, the active regulators can also be configured to serve different domains in the DSM, and thus some of the active regulators in a device or chip might be powered down or allowed to float their respective output voltages to enter deep-sleep mode.
It will be appreciated that a critical specification in any chip having such a dual regulator architecture is ‘wake-up time’ or the time it takes for the active regulator to come up to full power following sleep-mode.
A schematic diagram of a conventional active voltage regulator 100 is shown in FIG. 1. Referring to FIG. 1, the regulator 100 generally includes a two input operational amplifier (OPAMP 102) coupled to external power supplies VCC and VSS, and having an input 104 coupled to a reference voltage (VREF) and an output node 106 coupled to a voltage divider 108 including a vpwrcore made up of a chain of series connected N-channel metal-oxide-semiconductor (NMOS) transistors 110. A second input 112 to the OPAMP 102 provides feedback from the output node 106 through the voltage divider 108. A biasing transistor 114 provides biasing current (Ibias) through the OPAMP.
Typically, the regulator 100 further includes a compensation capacitor 116 directly connected to the output node 106 and the voltage divider 108 that must be charged when the regulator circuit is woken-up. Thus, one problem with conventional active voltage regulators 100 is the time it takes to charge this compensation capacitor 116, which accounts for the greater part of the wake-up time.
Another problem with conventional active voltage regulators 100 including a compensation capacitor 116, such as that shown in FIG. 1, is that the power used to charge the compensation capacitor is wasted each time the regulator toggles between standby and active mode.
One known method used to improve the wake-up time uses adaptive biasing configured to sense changes in the load current and alter an operating current of the regulator 100 in response, thereby enabling a more rapid charging of the compensation capacitor 116. Referring to FIG. 1, an adaptive biasing stack 118 typically includes a number of series connected MOS transistors coupled in parallel with the OPAMP 102 and the biasing transistor 114, and is configured to bias the voltage regulator 100 at a relatively low operating current for steady-state operation, while increasing the current during the transients, thereby improving the transient responses of the regulator.
Although the adaptive biasing stack 118 can improve wake-up time it does not solve the problem with wasting of power used to charge the compensation capacitor 116. In addition, adaptive biasing introduces a number of drawbacks or disadvantages including design complexity, overshooting on the output voltage, and the need for extra verification and/or mismatch concerns for the transistors in the adaptive biasing stack, which can result in either instability or increased quiescent current. Moreover, adaptive biasing does not work in headroom limited designs, such as pumped NGATE designs in which a first stage of the OPAMP operates on the pump as the adaptive biasing current needs to be controlled to prevent collapse of pump.
Accordingly, there is a need for a voltage regulator and method of using the same that reduces wakeup-time and power consumption in switching a device from standby or sleep-mode to active mode. It is further desirable that the voltage regulator and method eliminate the complex circuitry and potential instability problems due to transistor mismatch associated with adaptive biasing.